module RISC_SPM #(
	`include "C:/Users/gaoji/Desktop/RISC_SPM/src/para_def.v"
)(
	input clk, rst_n
);

	wire 			      ctrl2proc_load_R0;
	wire			      ctrl2proc_load_R1;
	wire				  ctrl2proc_load_R2;
	wire				  ctrl2proc_load_R3;
	wire				  ctrl2proc_load_PC;
	wire			      ctrl2proc_load_IR;
	wire				  ctrl2proc_load_reg_Y;
	wire				  ctrl2proc_load_reg_Z;
	wire				  ctrl2proc_load_add_R;
	wire				  ctrl2proc_inc_PC;
	wire [SEL1_WD -1:0]   ctrl2proc_mux1_sel_to_bus1;
	wire [SEL2_WD -1:0]   ctrl2proc_mux2_sel_to_bus2;
	
	wire				  ctrl2mem_write;
	wire [WORD_WD -1:0]   mem2proc_data;
	
	wire [WORD_WD -1:0]   proc2ctrl_instruction;
	wire 			      proc2ctrl_zero_flag;
	
	wire [ADDR_WD -1:0]   proc2mem_addr;
	wire [WORD_WD -1:0]   proc2mem_data;
	
	ctrl_unit U_CTRL(
		.load_R0(ctrl2proc_load_R0), 
		.load_R1(ctrl2proc_load_R1), 
		.load_R2(ctrl2proc_load_R2), 
		.load_R3(ctrl2proc_load_R3),
		.load_PC(ctrl2proc_load_PC), 
		.load_IR(ctrl2proc_load_IR),
		.load_reg_Y(ctrl2proc_load_reg_Y),
		.load_reg_Z(ctrl2proc_load_reg_Z),
		.load_add_R(ctrl2proc_load_add_R),
		.inc_PC(ctrl2proc_inc_PC),	
		.mux1_sel_to_bus1(ctrl2proc_mux1_sel_to_bus1),
		.mux2_sel_to_bus2(ctrl2proc_mux2_sel_to_bus2),
	
		.write(ctrl2mem_write),
	
		.instruction(proc2ctrl_instruction),
		.zero_flag(proc2ctrl_zero_flag),
		.clk(clk),
		.rst_n(rst_n)
	);
	
	processing_unit U_PROCESSING(
		.instruction(proc2ctrl_instruction),
		.zero_flag(proc2ctrl_zero_flag),
	
		.addr(proc2mem_addr),
		.bus1(proc2mem_data),
	
		.mem_word(mem2proc_data),
		.load_R0(ctrl2proc_load_R0), 
		.load_R1(ctrl2proc_load_R1), 
		.load_R2(ctrl2proc_load_R2), 
		.load_R3(ctrl2proc_load_R3),
		.load_PC(ctrl2proc_load_PC), 
		.load_IR(ctrl2proc_load_IR),
		.load_reg_Y(ctrl2proc_load_reg_Y),
		.load_reg_Z(ctrl2proc_load_reg_Z),
		.load_add_R(ctrl2proc_load_add_R),
		.inc_PC(ctrl2proc_inc_PC),
		.mux1_sel_to_bus1(ctrl2proc_mux1_sel_to_bus1),
		.mux2_sel_to_bus2(ctrl2proc_mux2_sel_to_bus2),
		.clk(clk), 
		.rst_n(rst_n)
	);
	
	mem_unit #(.DISPLAY_EN(1)) U_MEM(
		.data_out(mem2proc_data),
		.data_in(proc2mem_data),
		.addr_in(proc2mem_addr),
		.write_en(ctrl2mem_write),
		.clk(clk),
		.rst_n(rst_n)
	);

endmodule